Design Verification Engineer

Primary Responsibilities 
- Verifying the design, architecture and micro-architecture using advanced verification methodologies 
- Defining the verification scope and contributing to the development of the verification infrastructure 
- Collaborating with architects, designers, and software engineers across sites to accomplish verification targets 

- A BS degree in Electrical Engineering, Computer Science or other equivalent disciplines with > 5 years of relevant work or research experience, or a MS degree of the above areas with > 2 years of similar experience. 
- Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies - Fluency in Object Oriented Programming with C++ and/or SystemVerilog 
- Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB), and methodologies (UVM or equivalent) 
- Passionate about debugging and comprehensive problem-solving skills - High proficiency in English - both orally and in writing form. 
- Excellent communication skills; both articulate and a good listener. 
- Self-driven, result-oriented; able to multi-task and determine priorities. 
- A proven fast learner and a team player. 
- Experience of working with foreign coworkers and remote teams is a plus. 

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