RTL Designer

Primary Responsibilities 
- Design RTL for our CPU-centric Machine Learning ASIC chip - Optimize timing and power consumption 
- Support functionality debug in simulation and emulation 
- Write timing/power constraint for the design 

- MS or PhD degree in Electrical Engineering, Computer Science, Physics, Mathematics or equivalent disciplines. 
- MS with > 2 years of industrial experience; more experiences and capability will correspond to higher job levels. 
- Excellent RTL design skills with System Verilog. 
- Good scripting skills with Python/Perl/Tcl. 
- Solid understanding of low power optimization. 
- Proficient communication in English - both orally and in writing form. 
- Self-driven, result-oriented; able to multi-task and determine priorities. 
- A proven fast learner and a team player. 

- Knowledge and experience with RISC-V ISA is highly desired. 
- Knowledge about CPU architecture and memory hierarchy. 
- Experience of working with foreign coworkers and remote teams is a plus. 

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