Fungible is defining data-centric computing, both in terms of software and in terms of hardware (with its DPU).
As senior modeling engineer, you will be responsible for behavioral modeling of various aspect of this chip and defining the architecture/protocols that will revolutionize the performance, economics, and security of data centers at all scales. You will develop system level models to validate hardware behavior, run simulations, debug, gather statistics, evaluate performance under various traffic loads and provide feedback to designers. You will work with cross-functional teams including Hardware RTL Design team and Hardware DV team. You will also be responsible for integrating RTL into the model and co-simulating the system on an emulation platform.
This is a leadership role that requires a highly motivated individual with excellent technical and leadership skills – you will be responsible for setting the direction of the modeling work and delivering actionable results in timely manner.
Skills, Education, and Experience Required
- Minimum BS in Electrical Engineering or equivalent degree, PhD/Master’s preferred
- Deep understanding of networking, network architectures and system interface protocols
- HW modeling, architectural and performance validation experience
- Proficiency in algorithms and data structures
- Experience with scripting in Python and/or Perl
- Knowledge of C / C++
- Proven track record with the definition and development of complex SoCs
- Self-motivated and able to work effectively both independently and in a team
Additional Success Factors
- Experience with Omnet++ or other network simulator
- Experience with RTL design/verification and debug
- Knowledge of Python libraries for data visualization or equivalent
- Strong knowledge of Verilog / System Verilog
- Solid debugging/problem solving skills
- Ability to proactively take on responsibilities and ready to work in a start-up environment