Verification Engineer

Central to our mission is a highly programmable chip.  As part of the verification team, you will be responsible for independently creating leading edge constrained-random verification environments and using them to drive functional correctness of innovative designs. 
 
Key Qualifications
  • BS in Electrical Engineering or equivalent degree
  • 8+ years of experience in ASIC/SoC verification with SV/UVM environments 
  • In-depth knowledge of verification flows
  • Clear understanding of constrained random verification process, functional coverage, assertion methodology and philosophy
  • Team player with excellent communication skills and the desire to take on diverse challenges
 
Additional Success Factors
  • Advanced knowledge of CPU, cache hierarchy, & SoC architecture/design
  • Experience in verifying Ethernet, TCP/IP, PCIe and other industry standard protocols
  • Experience with modeling in C/C++
  • Knowledge of formal verification, hardware emulation
  • Startup experience
 
Keywords 
Silicon, chip, SoC, ASIC, processor, cache, CPU, GPU, fabric, networking, SSD, architecture, design, verification, CAD tools, x86, ARM, MIPS

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