Qualification/Experience/Skills Required
- Hands-on experience performing block level timing closure on advanced FinFET processes (14/16nm or newer)
- Hands-on experience with some steps in block level physical design (synthesis to GDS)
- Synopsys (ICC2) and/or Cadence (Innovus) physical design tools
- 2-5 years’ industry experience, BS EE
Roles & Responsibilities
- Under close supervision, assist, research, design, develop and test electronic circuits,
components, and chips in CPU, telecommunication, networking, storage and graphic
industry.
- Day to day responsibilities for the position includes physical design implementation,
floor planning, place & route, clock distribution, timing closure, power and signal
integrity analysis.
- Block level physical design activities for one or more blocks.