Senior SerDes Design Engineer

GENERAL DESCRIPTION
The High-Speed SerDes Design Engineer is responsible for the development of high-speed transceiver elements, such as TIAs, limiting amplifiers, I/Os, equalizers, high-speed CML, and other SerDes/CDR/PLL building blocks. Specific tasks include design, verification, layout, characterization, and system-level modeling of SerDes components for both electrical and optical communication mediums. You will work as a part of a small IC design team in a dynamic startup environment. The ideal candidate is a hands-on self-starter who is able to develop design specifications based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.

REQUIREMENTS
  • M.S or Ph.D in Electrical Engineering
  • 4+ years of working/research experience in high-speed design and/or design of SerDes components such as CTLEs, TIAs, PLLs, DFEs, etc.
  • Have experience designing in advanced CMOS (65nm or below) at data rates of at least 10Gb/s and/or RF circuits operating at 5GHz or above
  • Proficient with Cadence design environment and mixed-signal simulation (ADE, Layout, Spectre)

THE IDEAL CANDIDATE WILL ALSO HAVE
  • A system-level understanding of both analog frontend and digital link backend for SerDes systems
  • A good understanding of high-speed layout considerations, such as parasitics, crosstalk isolation, supply and bias distribution, etc.
  • Proficiency with chip-level or board-level EM simulation (such as EMX or HFSS)
  • Experience with precision analog and mixed-signal circuits
  • Programming experience in Python

ABOUT AYAR LABS
At Ayar Labs we are lighting up electronics for a brighter future. With our deep ties to MIT and UC Berkeley, and our commitment to hiring the best engineers in photonics and electronics, joining our team gives you the opportunity to collaborate with brilliant people on challenging, paradigm-shifting work. Our optical I/O technology removes the bottlenecks created by today’s electrical I/O, making it possible to continue the computing system performance scaling that Moore’s Law enabled until now. We have a commitment to win big in the marketplace based on the strengths of our technology, and we approach everything with an eye to massive scalability. We believe that deep cross-collaboration between teams facilitated by honest, open debate is the best way to achieve big wins, leveraging our patent portfolio which promises products that deliver orders of magnitude improvements in latency, bandwidth density, and power consumption. We offer a comprehensive benefits plan designed to keep our team healthy and happy. 

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