ESD Contractor

Hello,
Hope you are doing well.
 
I came across your resume on Job board and am reaching out to you because I feel you might be a great match for a “ESD Contractor”  opening that I am looking to fill for my client in “Santa Clara, CA”. “This position is with a  high growth company”  the project duration is for approximately 6+ months with high possibilities of extension. I would appreciate a few moments of your time to go over the job description and see if this position might be a mutual fit
 
Central R&D team at ON Semiconductor seek a strong device engineer to support ESD activities
related to Intelligent Sensing Group (ISG) imaging products. ON is a Fortune-500 automotive IC
products supplier, with over 34,000 employees world-wide. ISG division design and fabricate CMOS
Image Sensors, Radar & Lidar solutions, serving Automotive, Industrial, Consumer, and Medical
sectors. The successful candidate will be responsible to conduct tools based ESD verification of mixed
signal IO floor-plans, construct ESD architectures, construct die and package interconnects strategy for
advanced CMOS & Mixed-Signal process technologies.
 
This position is in device methodology group located in Santa Clara, CA. It involves using ESD
verification tools (such as Magwel ESDi, Ansys PathFinder) during product floor-planning and data-
base releases. Work includes IO-Ring construction, ESD cells & TLP model library support, lab
characterizations, product failure analysis, and improving CDM & HBM performance where necessary.
Technologies cover Silicon, Si-Ge, with clamp structures involving Bipolar & CMOS device types.
Image-Sensor solutions span single-wafer, multi-wafer-stack, and package-die solutions that must
withstand die-level and system-level product handling requirements. The work will cover reliability
studies and device and structure improvements, design of test structures, topological and electrical
design rule generation and verification for existing and new silicon technology developments.
 
Responsibilities:
• IO-Banks and Full-Chip-IO verification using CAE ESD tools.
• Constructing Cell & Model libraries to facilitate tools based ESD verification.
• ESD architectures for multiple power domain, ~100 pin count devices.
• Ensure 3 rd party IP ESD robustness & compatibility with ISG ESD verification.
• Device simulations to study performance and reliability requirements.
• Design of test structures and characterization.
• Support development and implementation of design rule checks.
• Participate in design review activities from device perspective.
• Lab work to evaluate device performance under discharge-pulses.
 
Qualifications
Requirements:
• College degree MS/PhD in Electrical Engineering.
• Hands on experience using CAE tools for ESD verification (Ex. Magwel, Ansys).
• Strong understanding of ESD architectures & IO Constructions.
• Knowledge of Cadence design environment (layout and schematic).
• Exposure to IO layout with integration of IO-protection structures.
• Exposure to semiconductor foundry technologies and PDK’s.
• Ability to characterize semiconductor devices with test analyzer equipment.
• Good written and oral communication skills.
• Ability for independent work, and be an effective team player.
 
Preferred:
• BS/6+ yrs or MS/4+ years in Electrical Engineering, with 3 years of related experience.
• Use of Magwel ESDi tool for ESD verification and product release.
• Good understanding of semiconductor device physics and circuits.
• Knowledge / expertise of on-chip HBM, CDM ESD protections.
 
• Experience in implementing Foundry ESD offerings on > 50 pin mixed signal chips.
 
Regards
 
Ronny Dsouza
APN Software Services INC
39899 Balentine Drive, Suite 385, Newark, CA 94560
ronny@apninc.com
Phone: 510-870-8707

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