Design for Test Engineer/DFT Engineer
Location: Boston, MA or San Jose, CA
Duration: 6 Months
Skill Set:
BS, MS, PhD, in electrical or computer engineering
Expertise with tools for scan design, ATPG, Memory BIST and boundary scan is required
Experience with test tools and simulators from one or more EDA vendor is required
Experience working with multiple complex chips at 28 nm and below
Proficiency with Linux, Perl and TCL is required
Good problem solving and debugging skills
Experience :
5+years
Job Description :
Responsible across the full spectrum of Design For Test (DFT) solutions for complex chips on leading edge technologies
Insert scan, Memory BIST and boundary scan into designs, and create both ATPG and functional patterns
Run test suites and debug chips in test labs
Write tools and scripts in Perl and other scripting languages to enhance the DFT process
Work on complex high performance and low power designs
Thank you,
Sachin P.,
sachin@apninc.com