Location: San Jose CA
Duration: 3 Months
As a Physical Implementation Engineer, you will play a leading ownership role in the physical design domain for developing cutting-edge image sensor products. You will work on all aspects of the RTL-to- GDS flow including chip sign-off activities.
You need to work closely with cross-functional teams like Digital logic design, Analog Design, IP Design, Packaging and Product/Test Engineering in determining architecture/specification, design integration and post-silicon validation support of the products.
BSEE required with 10 years of related work experience in physical design.
Solid understanding of ASIC physical design flow from synthesis to tape-out includinghands-on experience in synthesis, floor planning, LVS/DRC, die area estimation, integration of hard IPs, ECO implementation, constraints management etc.
Experience leading the full chip APR/Implementation/Integration, preferably with technical oversight of a small team of engineers.
Experience in the low-power design methodology is a big plus.
Expertise on Cadence PNR flow
Hands-on experience on EDA tools: Design Compiler, Encounter/Innovus (ICC/ICCII highly preferable), Conformal-LEC/Formality, Calibre LVS and DRC, Primetime-SI, Redhawk/Prime-Rail/Voltus.
Solid understanding of the library views used in the implementation process (lef, lib, def)
Self-motivated and an ability to take ownership of the physical design activities.
Excellent communication and interpersonal skills.
Strong programming skills in TCL/Perl, methodology development and rollout processes are a plus.